Wang Tao, Huawei's deputy chairman and rotating chairman, shared the latest progress on the company's Ascend chips at Huawei Connect 2026 on September 17, saying that development of the Ascend 960 chip is ahead of schedule and that its performance has doubled.
According to the company, the Ascend 960DT supports 2 PFLOPS of FP8 and 4 PFLOPS of FP4 computing power, with on-chip HBM capacity of up to 288 GB and memory access bandwidth of up to 9.6 TB/s. It is set to be ready in the first quarter of 2027, three quarters earlier than originally targeted. The Ascend 960PR, which supports 2 PFLOPS of FP8 and 8 PFLOPS of FP4 computing power, will be ready in the third quarter of 2027, one quarter ahead of the original plan.
On this basis, Huawei's Ascend chips will maintain a "one generation per year" evolution cadence, with the Ascend 970 and Ascend 980 to be launched in 2028 and 2029, respectively. Leveraging innovation guided by the Tau (τ) Law, the company aims to continue doubling computing power specifications, while also achieving substantial improvements in memory access bandwidth, memory access capacity and interconnect bandwidth.